1. Field of the Invention
The present invention relates to a semiconductor structure and a fabrication method thereof. More particularly, the present invention relates to a stacked chip structure having patterned polymer layers and a fabrication method of the stacked chip structure.
2. Description of Related Art
In modern information era, consumers continuously pursue electronic products with high speed, outstanding quality and multiple functions. The design of exterior appearances of the electronic products reveals a trend of light weight, thinness, and small size. To comply with said demand, a stacked chip structure has been developed recently. A plurality of stacked chips in the stacked chip structure is bonded and electrically connected to one another. Therefore, the stacked chip structure features a fast transmission speed, a short transmission path and favorable electric characteristics, and a size and an area of the stacked chip structure are further reduced. As a result, the stacked chip structure has been extensively applied to various kinds of electronic products and has become a mainstream product in future market.
As shown in FIG. 1, a method of forming the stacked chip structure mainly includes fabricating a via 12 at the same position on each chip 10. Besides, an electroplating process for the high-aspect-ratio via 12 is implemented to fill a conductive material 20 into the via 12, and solder bumps 30 are disposed on each of the vias 12. Moreover, the solder bumps 30 can be electrically connected to the conductive material 20 in the corresponding via 12. Next, an adhesive layer 40 is disposed on each of the chips 10. Thereafter, the chips 10 are stacked, such that each of the chips 10 can be bonded through the adhesive layer 40 of each of the chips 10. In the meantime, each of the chips 10 is connected to the conductive material 20 of the adjacent chips 10 through the solder bumps 30, so as to accomplish electrical connection between the chips 10. After that, a underfill 50 is filled between the chips 10 to protect the solder bumps 30. Herein, the method of connecting the solder bumps 30 of each of the chips 10 to the conductive material 20 of the adjacent chips 10 mostly includes heating the solder bumps 30 of each of the chips 10, such that the solder bumps 30 of each of the chips 10 are softened and thereby are connected to the conductive material 20 of the adjacent chips 10.
However, the underfill 50 is a bad conductor, thus negatively affecting heat dissipation efficacy among the chips 10. Besides, as the stacked structure is formed by stacking wafers (not shown), it is rather difficult to fill the space between the wafers with the underfill 50, and hence holes may be formed between the underfill 50 and the wafers. When air exists in the holes, a popcorn effect is apt to be induced by heating the stacked structure. In addition, the solder bumps 30 of each of the chips 10 are likely to be softened when heated, such that the heat-softened solder bumps 30 are apt to overflow onto the adjacent solder bumps 30, resulting in circuit shortage of the adjacent solder bumps 30. In addition, when an arrangement of the solder bumps 30 on the chips 10 follows the trend of fine pitch, the shortened distance between the solder bumps 30 may easily give rise to the overflow of the solder bumps 30 onto the adjacent solder bumps 30 during a heating process, which is likely to cause circuit shortage.